TPARMD=ODD, RSYNCEN=DISABLED, RSTRTEN=DISABLED, RPARMD=ODD, TINVEN=DISABLED, RDATLN=5_BITS, RSCEN=DISABLED, TSTPMD=0P5_STOP, TSTRTEN=DISABLED, TIRDAEN=DISABLED, TSYNCEN=DISABLED, TDATLN=5_BITS, TSCEN=DISABLED, TPAREN=DISABLED, RIRDAEN=DISABLED, RINVEN=DISABLED, RSTPEN=DISABLED, RPAREN=DISABLED, RSTPMD=0P5_STOP, TSTPEN=DISABLED
Module Configuration
| RSTRTEN | Receiver Start Enable. 0 (DISABLED): Do not expect a start bit during receptions. 1 (ENABLED): Expect a start bit during receptions. |
| RPAREN | Receiver Parity Enable. 0 (DISABLED): Do not expect a parity bit during receptions. 1 (ENABLED): Expect a parity bit during receptions. |
| RSTPEN | Receiver Stop Enable. 0 (DISABLED): Do not expect stop bits during receptions. 1 (ENABLED): Expect stop bits during receptions. |
| RSTPMD | Receiver Stop Mode. 0 (0P5_STOP): 0.5 stop bit. 1 (1_STOP): 1 stop bit. 2 (1P5_STOP): 1.5 stop bits. 3 (2_STOP): 2 stop bits. |
| RPARMD | Receiver Parity Mode. 0 (ODD): Odd Parity. 1 (EVEN): Even Parity. 2 (MARK): Set (Parity = 1). 3 (SPACE): Clear (Parity = 0). |
| RDATLN | Receiver Data Length. 0 (5_BITS): 5 bits. 1 (6_BITS): 6 bits. 2 (7_BITS): 7 bits. 3 (8_BITS): 8 bits. 4 (9_BITS_STORED): 9 bits. The 9th bit is stored in the FIFO (normal mode). 5 (9_BITS_MATCH): 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD). |
| RSCEN | Receiver Smartcard Parity Response Enable. 0 (DISABLED): The receiver does not send a Smartcard parity error response. 1 (ENABLED): The receiver sends a Smartcard parity response. |
| RIRDAEN | Receiver IrDA Enable. 0 (DISABLED): The receiver does not operate in IrDA mode. 1 (ENABLED): The receiver operates in IrDA mode. |
| RINVEN | Receiver Invert Enable. 0 (DISABLED): Do not invert the RX pin signals (the RX idle state is high). 1 (ENABLED): Invert the RX pin signals (the RX idle state is low). |
| RSYNCEN | Receiver Synchronous Mode Enable. 0 (DISABLED): The receiver operates in asynchronous mode. 1 (ENABLED): The receiver operates in synchronous mode. |
| TSTRTEN | Transmitter Start Enable. 0 (DISABLED): Do not generate a start bit during transmissions. 1 (ENABLED): Generate a start bit during transmissions. |
| TPAREN | Transmitter Parity Enable. 0 (DISABLED): Do not send a parity bit during transmissions. 1 (ENABLED): Send a parity bit during transmissions. |
| TSTPEN | Transmitter Stop Enable. 0 (DISABLED): Do not send stop bits during transmissions. 1 (ENABLED): Send stop bits during transmissions. |
| TSTPMD | Transmitter Stop Mode. 0 (0P5_STOP): 0.5 stop bit. 1 (1_STOP): 1 stop bit. 2 (1P5_STOP): 1.5 stop bits. 3 (2_STOP): 2 stop bits. |
| TPARMD | Transmitter Parity Mode. 0 (ODD): Odd Parity. 1 (EVEN): Even Parity. 2 (MARK): Set (Parity = 1). 3 (SPACE): Clear (Parity = 0). |
| TDATLN | Transmitter Data Length. 0 (5_BITS): 5 bits. 1 (6_BITS): 6 bits. 2 (7_BITS): 7 bits. 3 (8_BITS): 8 bits. 4 (9_BITS_FIFO): 9 bits. The 9th bit is taken from the FIFO data (normal mode). 5 (9_BITS_TBIT): 9 bits. The 9th bit is set by the value of TBIT (fixed mode). |
| TSCEN | Transmitter Smartcard Parity Response Enable. 0 (DISABLED): The transmitter does not check for a Smartcard parity error response. 1 (ENABLED): The transmitter checks for a Smartcard parity error response. |
| TIRDAEN | Transmitter IrDA Enable. 0 (DISABLED): Disable IrDA transmit mode. 1 (ENABLED): Enable IrDA transmit mode. |
| TINVEN | Transmitter Invert Enable. 0 (DISABLED): Do not invert the TX pin signals (the TX idle state is high). 1 (ENABLED): Invert the TX pin signals (the TX idle state is low). |
| TSYNCEN | Transmitter Synchronous Mode Enable. 0 (DISABLED): The transmitter operates in asynchronous mode. 1 (ENABLED): The transmitter operates in synchronous mode. |